Processor-Core Based Design and Test

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DC Field	Value	Language
dc.contributor.author	Marwedel, Peter	de
dc.date.accessioned	2004-12-06T12:57:12Z	-
dc.date.available	2004-12-06T12:57:12Z	-
dc.date.created	1997	de
dc.date.issued	1998-07-04	de
dc.identifier.uri	http://hdl.handle.net/2003/2758	-
dc.identifier.uri	http://dx.doi.org/10.17877/DE290R-5201	-
dc.description.abstract	This tutorial responds to the rapidly increasing use of various cores for implementing systems-on-a-chip. It specifically focusses on processor cores. We will give some examples of cores, including DSP cores and application-specific instruction-set processors (ASIPs). We will mention market trends for these components, and we will touch design procedures, in particular the use compilers. Finally, we will discuss the problem of testing core-based designs. Existing solutions include boundary scan, embedded in-circuit emulation (ICE), the use of processor resources for stimuli/response compaction and self-test programs.	en
dc.format.extent	119443 bytes	-
dc.format.extent	133097 bytes	-
dc.format.mimetype	application/pdf	-
dc.format.mimetype	application/postscript	-
dc.language.iso	en	de
dc.publisher	Universität Dortmund	de
dc.subject.ddc	004	de
dc.title	Processor-Core Based Design and Test	en
dc.type	Text	de
dc.type.publicationtype	conferenceObject	-
dcterms.accessRights	open access	-
Appears in Collections:	Entwurfsautomatisierung für Eingebettete Systeme

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1997-aspdactut.ps		116.64 kB	Postscript	View/Open
aspdactut.pdf		129.98 kB	Adobe PDF	View/Open

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