System level modeling and design with the SpecC language - Dömer, Rainer (Universität Dortmund, 2000)
The semiconductor roadmap estimates the design complexity for digital systems to continue to increase according to Moore's law. In the next years, embedded systems with 10ths of millions of transistors on one chip will be standard technology. SystemonChip (SOC) designs will integrate processor cores, memories and special purpose custom logic into a complete system fitting on a single die. However, the increased complexity of SOC designs requires more effort, more efficient tools and new methodologies. Increasing the design time is not an option due to market pressures. Systemlevel design reduces the complexity of the design models by raising the level of abstraction. Starting from an abstract specification model, the system is stepwise refined with the help of computeraided design (CAD) tools. Using codesign techniques, the system is partitioned into hardware and software parts and finally implemented on a target architecture. Established design methodologies for behavioral synthesis and standard software design are utilized. However, moving to higher abstraction levels is not sufficient. The key to cope with the complexity involved with SOC designs is the reuse of Intellectual Property (IP). The integration of complex components, which are predesigned and welltested, drastically reduces the design complexity and, thus, saves design time and allows a shorter timetomarket. Since the idea of IP reuse promises great benefits, it must become an integral part in the system design methodology. Furthermore, the use of IP components must be directly supported by the design models, the tools and the languages being used throughout the design process. For example, it must be easy to insert and replace IP components in the design model (``plugandplay''). This work addresses the main issues in SOC design, namely the system design methodology, systemlevel modeling, and the specification language. First, an IPcentric system design methodology is proposed which is based on the reuse of IP. It allows the reuse and integration of IP components at any level and at any time during the design process. Starting with an abstract executable specification of the system, architecture exploration and communication synthesis are performed in order to map the design model onto the target architecture. At any stage, the systems functionality and its characteristics can be evaluated and validated. The model being used in the methodology to represent the system must meet system design requirements. It must be suitable to represent abstract properties at early stages as well as specific details about design decisions later in the design process. In order to support IP, the model must clearly separate communication from computation. In this work, a hierarchical model is described which encapsu lates computation and communication in separate entities, namely behaviors and channels. This model naturally supports reuse, integration and protection of IP. In order to formally describe a design model, a language should be used which directly represents the properties and characteristics of the model. This work presents a newly developed language, called SpecC, which allows to map modeling concepts onto language constructs in a one to one fashion. Unlike other systemlevel languages, the SpecC language precisely covers the unique requirements for embedded systems design in an orthogonal manner. Built on top of the C language, the defacto standard for software development, SpecC supports additional concepts needed in hardware design and allows IPcentric modeling. Recently, the SpecC language has been proposed as a standard systemlevel language for adoption in industry by some of Japan's toptier electronics and semiconductor companies. The proposed methodology and the SpecC language have been implemented in the SpecC design environment. In a graphical framework, the SpecC design environment integrates a set of CAD tools which support systemlevel modeling, design validation, design space exploration, and (semi) automatic refinement. The framework and all tools rely on a powerful, central design representation, the SpecC Internal Representation (SIR). Using the SpecC design environment, the IPcentric methodology has been successfully applied to several designs of industrial size, including a GSM vocoder used in mobile telecommunication.
Keywords: Systemdesign; embedded system; SpecC; System-level design; VLSI; System-on-chip; intellectual property; Schaltungsentwurf; Spezifikationssprache; Hierarchisches Modell; Formale Spezifikation; 004