Circuit Analysis and Design using Evolutionary Algorithms
| dc.contributor.author | Burwick, Christian | de |
| dc.contributor.author | Goser, Karl | de |
| dc.contributor.author | Thomas, Marc | de |
| dc.date.accessioned | 2004-12-06T12:55:57Z | |
| dc.date.available | 2004-12-06T12:55:57Z | |
| dc.date.created | 2000 | de |
| dc.date.issued | 2004-05-12 | de |
| dc.description.abstract | This paper focuses on electronic design at circuit level. The use of evolutionary algorithms to this application is discussed and a trade off to existing approaches is investigated. The design and analyzing task at this level is described in detail. As example a 1-bit full adder design in static CMOS is inspected with regard to power consumption and delay. In algorithmic scope both, single- and multi-objective optimization are regarded here. Finally some concluding remarks are given in section 6. ircuit Optimization Electronic design at circuit-level is a numeric adjustment process to meet constraints and goals on a fixed structure. Parameter extraction and variation, simulation, and result | en |
| dc.format.extent | 152926 bytes | |
| dc.format.extent | 481757 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.format.mimetype | application/postscript | |
| dc.identifier.uri | http://hdl.handle.net/2003/2728 | |
| dc.identifier.uri | http://dx.doi.org/10.17877/DE290R-5181 | |
| dc.language.iso | en | de |
| dc.publisher | Universität Dortmund | de |
| dc.subject.ddc | 004 | de |
| dc.title | Circuit Analysis and Design using Evolutionary Algorithms | en |
| dc.type | Text | de |
| dc.type.publicationtype | workingPaper | |
| dcterms.accessRights | open access |