Register-Constrained Address Computation in DSP Programs

Full metadata record

DC Field	Value	Language
dc.contributor.author	Basu, Anupam	de
dc.contributor.author	Leupers, Rainer	de
dc.contributor.author	Marwedel, Peter	de
dc.date.accessioned	2004-12-06T12:57:13Z	-
dc.date.available	2004-12-06T12:57:13Z	-
dc.date.created	1998	de
dc.date.issued	1998-07-02	de
dc.identifier.uri	http://hdl.handle.net/2003/2760	-
dc.identifier.uri	http://dx.doi.org/10.17877/DE290R-3198	-
dc.description.abstract	This paper describes a new code optimization technique for digital signal processors (DSPs). One important characteristic of DSP algorithms are iterative accesses to data array elements within loops. DSPs support efficient address computations for such array accesses by means of dedicated address generation units (AGUs). We present a heuristic technique which, given an AGU with a fixed number of address registers, minimizes the number of instructions needed for array address computations in a program loop.	en
dc.format.extent	134602 bytes	-
dc.format.extent	99069 bytes	-
dc.format.mimetype	application/pdf	-
dc.format.mimetype	application/postscript	-
dc.language.iso	en	de
dc.publisher	Universität Dortmund	de
dc.subject.ddc	004	de
dc.title	Register-Constrained Address Computation in DSP Programs	en
dc.type	Text	de
dc.type.publicationtype	conferenceObject	-
dcterms.accessRights	open access	-
Appears in Collections:	Entwurfsautomatisierung für Eingebettete Systeme

Files in This Item:

File	Description	Size	Format
1998-date-BLM.ps		96.75 kB	Postscript	View/Open
date-blm.pdf		131.45 kB	Adobe PDF	View/Open

This item is protected by original copyright

Show simple item record

This item is protected by original copyright rightsstatements.org