Fabrication of steep slope carbon nanotube transistors on novel multi-gate substrates

Abstract

The need for highly integrated low-power transistors has rapidly increased over the last decades. The very effective downscaling and optimization of metal-oxide-semiconductor field-effect transistors (MOSFETs) have initiated the advanced technological environment of today. However, the physical limitations of those devices are restricting its further development to a certain point which has already been reached or will be in the very near future. The thesis focuses on steep slope transistor technology, designated to potentially replace MOSFET architectures. The work includes the design and fabrication of a so-called buried triple gate platform (BTG), integrating three graphene/metal gates to implement individually adjustable electrostatic doping profiles. The wafer-scaled manufacturing process involves optical lithography, physical and chemical vapor deposition techniques, reactive ion etching and wet etching structuring procedures. With the deposition of carbon nanotubes and the subsequent connection to source and drain terminals, Tunnel-FET devices are fabricated to demonstrate the feasibility of the architecture. Moreover, similar devices called energy filtering FETs are manufactured using an existing buried multi gate platform (BMG). Providing 17 mutually insulated and individually addressable gates, the platform enables the generation of periodic potential barriers creating a so-called superlattice. The emerging miniband allows for tunneling at low energies while preventing hot electron injection from the Boltzmann tail, hence the term energy filtering FET. The final fabrication of the transistors is carried out by high-resolution electron-beam lithography on either platform. Subsequent static electrical measurements demonstrate transistor characteristics and the working principle of the architectures for electrostatic doping of low- dimensional materials. Both platforms are universal and can be used for application and analysis of electrostatic doping of various 1D and 2D materials. The achieved results in this work can be considered to be a successful validation of the concept for steep slope transistor devices with the potential to obtain a central role in future low-power applications.