Memory-aware mapping strategies for heterogeneous MPSoC systems
| dc.contributor.advisor | Marwedel, Peter | |
| dc.contributor.author | Holzkamp, Olivera | |
| dc.contributor.referee | Teubner, Jens | |
| dc.date.accepted | 2017-03-16 | |
| dc.date.accessioned | 2017-05-08T14:20:56Z | |
| dc.date.available | 2017-05-08T14:20:56Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | Embedded systems, such as mobile phones, integrate more and more features, e.g. multiple cameras, GPS sensors and many other sensors and actuators. These kind of embedded systems are dealing with increasing complexity due to demands on performance and constraints in energy consumption. The performance on such systems can be increased by executing application tasks in parallel. To achieve this, multiprocessor systems-on-chip (MPSoC) devices were introduced. On the other side, the energy consumption of these systems has to be decreased, especially for battery-driven embedded systems. A reduction in energy consumption can be achieved by efficiently utilizing the hardware resources on these devices. MPSoC devices can be either homogeneous or heterogeneous. Homogeneous MPSoC devices usually contain the same type of processors with the same speed, i.e. clock frequency, and the same type and size of memories for each processor. In heterogeneous MPSoC devices, the processor types and/or clock frequencies and memory types and/or sizes may vary. During the last decade, research has dealt with optimizations for the efficient utilization of hardware resources on MPSoCs. Central issues are the extraction of parallelism from sequential code and the efficient mapping of the parallelized application tasks onto the processors of the system. A few frameworks have been developed which distribute parallelized application tasks to available processors while optimizing for one or more objectives such as performance and energy consumption. They usually integrate all required, foregoing steps such as the extraction of parallelized tasks from sequential code and the extraction of a task graph as input for the mapping optimization. These steps are performed either manually or in an automated way. These kind of frameworks help the embedded system designer to significantly reduce design time. Unfortunately, the influence of memories or memory hierarchies is neglected in mapping optimizations, even though it is a well-known fact that memories have a drastic impact on the runtime and energy consumption of the system. This dissertation investigates the effect of memory hierarchies in MPSoC mapping. Since a thread based application model is used, a thread graph extraction tool is introduced. Furthermore, two approaches for memory-aware mapping optimization for homogeneous and heterogeneous embedded MPSoC devices are presented. The thread graph extraction tool extracts a flat thread graph with important annotations for software requirements, hardware performance and energy consumption. This thread graph represents all required input information for the subsequent memory-aware mapping optimizations. Dependent on the complexity of the application, the designer can choose between a fine-grained and a coarse-grained thread graph and thus influence the overall design time. The first presented memory-aware mapping approach handles single objective optimizations, which reduce either the runtime or the energy consumption of the system. The second presented memory-aware mapping approach handles a multiobjective optimization, which reduces both, runtime and energy consumption. All approaches additionally reduce the work of the embedded system designer and thus the design time. They work in a fully automated way and are integrated within the MACCv2/MNEMEE tool flow. The MNEMEE tool flow also provides all required foregoing steps such as the parallelization of sequential application code. The presented evaluations show that considering memory mapping during MPSoC mapping optimization significantly reduces the application runtime and energy consumption. The single objective optimizations are able to achieve an average reduction in runtime by about 21% and an average reduction in energy consumption by about 28%. The multiobjective memory-aware mapping optimization achieves an average reduction in runtime by about 21% and an average reduction in energy consumption by about 26%. Both presented optimization approaches were validated for homogeneous and heterogeneous MPSoC devices. The results clearly show that neglecting the memory subsystem can lead to wasted optimization potential. | de |
| dc.identifier.uri | http://hdl.handle.net/2003/35958 | |
| dc.identifier.uri | http://dx.doi.org/10.17877/DE290R-17981 | |
| dc.language.iso | en | de |
| dc.subject | Memory optimization | de |
| dc.subject | MPSoCs | de |
| dc.subject | Thread mapping | de |
| dc.subject | Scratchpad memories | de |
| dc.subject | Homogeneous | de |
| dc.subject | Heterogeneous | de |
| dc.subject.ddc | 004 | |
| dc.subject.rswk | System-on-Chip | de |
| dc.subject.rswk | Chip-Multiprozessor | de |
| dc.subject.rswk | Multithreading | de |
| dc.subject.rswk | Parallelisierung | de |
| dc.subject.rswk | Speicherverwaltung | de |
| dc.subject.rswk | Mehrkriterielle Optimierung | de |
| dc.title | Memory-aware mapping strategies for heterogeneous MPSoC systems | de |
| dc.type | Text | de |
| dc.type.publicationtype | doctoralThesis | de |
| dcterms.accessRights | open access |