Memory carousel: LLVM-based bitwise wear leveling for nonvolatile main memory

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dc.contributor.authorHölscher, Nils
dc.contributor.authorHakert, Christian
dc.contributor.authorNassar, Hassan
dc.contributor.authorChen, Kuan-Hsun
dc.contributor.authorBauer, Lars
dc.contributor.authorChen, Jian-Jia
dc.contributor.authorHenkel, Jörg
dc.date.accessioned2023-10-11T06:27:35Z
dc.date.available2023-10-11T06:27:35Z
dc.date.issued2022-12-14
dc.description.abstractEmerging nonvolatile memory yields, alongside many advantages, technical shortcomings, such as reduced cell lifetime. Although many wear-leveling approaches exist to extend the lifetime of such memories, usually a tradeoff for the granularity of wear leveling has to be made. Due to iterative write schemes (repeatedly sense and write), wear out of memory in certain systems is directly dependent on the written bit value and thus can be highly imbalanced, requiring dedicated bit-wise wear leveling. Such a bit-wise wear leveling so far has only be proposed together with a special hardware support. However, if no dedicated hardware solutions are available, especially for commercial off-the-shelf systems with nonvolatile memories, a software solution can be crucial for the system lifetime. In this work, we propose entirely software-based bit-wise wear leveling, where the position of bits within CPU words in the main memory is rotated on a regular basis. We leverage the LLVM intermediate representation to adjust load and store operations of the application with a custom compiler pass. Experimental evaluation shows that the lifetime by applying local rotation within the CPU word can be extended by a factor of up to 21× . We also show that our method can incorporate with coarser-grained wear leveling, e.g., on block granularity and assist achievement of higher lifetime improvements.en
dc.identifier.urihttp://hdl.handle.net/2003/42131
dc.identifier.urihttp://dx.doi.org/10.17877/DE290R-23964
dc.language.isoende
dc.relation.ispartofseriesIEEE transactions on computer-aided design of integrated circuits and systems;42(8)
dc.rights.urihttps://creativecommons.org/licenses/by/4.0/de
dc.subjectBit rotationen
dc.subjectIntermediate representation (IR)en
dc.subjectLLVMen
dc.subjectNonvolatile main memoryen
dc.subjectWear levelingen
dc.subject.ddc004
dc.subject.rswkNichtflüchtiger Speicherde
dc.subject.rswkVerschleißfestigkeitde
dc.titleMemory carousel: LLVM-based bitwise wear leveling for nonvolatile main memoryen
dc.typeTextde
dc.type.publicationtypeArticlede
dcterms.accessRightsopen access
eldorado.secondarypublicationtruede
eldorado.secondarypublication.primarycitationN. Hölscher et al., "Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 8, pp. 2527-2539, Aug. 2023, doi: 10.1109/TCAD.2022.3228897.de
eldorado.secondarypublication.primaryidentifierDOI: 10.1109/TCAD.2022.3228897de

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