Using Constraint Logic Programming in Memory Synthesis for General Purpose
| dc.contributor.author | Beckmann, Renate | de |
| dc.contributor.author | Herrmann, Jürgen | de |
| dc.date.accessioned | 2004-12-06T12:57:01Z | |
| dc.date.available | 2004-12-06T12:57:01Z | |
| dc.date.created | 1997 | de |
| dc.date.issued | 1998-07-04 | de |
| dc.description.abstract | In this paper, we extend the set of library components which are usually considered in architectural synthesis by components with built-in chaining. For such components, the result of some internally computed arithmetic function is made available as an argument to some other function through a local connection. These components can be used to implement chaining in a data-path in a single component. Components with built-in chaining are combinatorial circuits. They correspond to ``complex gates in logic synthesis. If compared to implementations with several components, components with built-in chaining usually provide a denser layout, reduced power consumption, and a shorter delay time. Multiplier/accumulators are the most prominent example of such components. Such components require new approaches for library mapping in architectural synthesis. In this paper, we describe an IP-based approach taken in our OSCAR synthesis system. | en |
| dc.format.extent | 155254 bytes | |
| dc.format.mimetype | application/postscript | |
| dc.identifier.uri | http://hdl.handle.net/2003/2747 | |
| dc.identifier.uri | http://dx.doi.org/10.17877/DE290R-3072 | |
| dc.language.iso | en | de |
| dc.publisher | Universität Dortmund | de |
| dc.subject.ddc | 004 | de |
| dc.title | Using Constraint Logic Programming in Memory Synthesis for General Purpose | en |
| dc.type | Text | de |
| dc.type.publicationtype | workingPaper | |
| dcterms.accessRights | open access |