Register-Constrained Address Computation in DSP Programs
Loading...
Date
1998-07-02
Journal Title
Journal ISSN
Volume Title
Publisher
Universität Dortmund
Abstract
This paper describes a new code optimization technique for digital signal processors (DSPs). One important characteristic of DSP algorithms are iterative accesses to data array elements within loops. DSPs support efficient address computations for such array accesses by means of dedicated address generation units (AGUs). We present a heuristic technique which, given an AGU with a fixed number of address registers, minimizes the number of instructions needed for array address computations in a program loop.