Unlocking efficiency in BNNs: global by local thresholding for analog-based HW accelerators

Yayla, Mikail; Frustaci, Fabio; Spagnolo, Fanny; Chen, Jian-Jia; Amrouch, Hussam

Unlocking efficiency in BNNs: global by local thresholding for analog-based HW accelerators

dc.contributor.author	Yayla, Mikail
dc.contributor.author	Frustaci, Fabio
dc.contributor.author	Spagnolo, Fanny
dc.contributor.author	Chen, Jian-Jia
dc.contributor.author	Amrouch, Hussam
dc.date.accessioned	2024-06-28T08:28:34Z
dc.date.available	2024-06-28T08:28:34Z
dc.date.issued	2023-09-14
dc.description.abstract	For accelerating Binarized Neural Networks (BNNs), analog computing-based crossbar accelerators, utilizing XNOR gates and additional interface circuits, have been proposed. Such accelerators demand a large amount of analog-to-digital converters (ADCs) and registers, resulting in expensive designs. To increase the inference efficiency, the state of the art divides the interface circuit into an Analog Path (AP), utilizing (cheap) analog comparators, and a Digital Path (DP), utilizing (expensive) ADCs and registers. During BNN execution, a certain path is selectively triggered. Ideally, as inference via AP is more efficient, it should be triggered as often as possible. However, we reveal that, unless the number of weights is very small, the AP is rarely triggered. To overcome this, we propose a novel BNN inference scheme, called Local Thresholding Approximation (LTA). It approximates the global thresholdings in BNNs by local thresholdings. This enables the use of the AP through most of the execution, which significantly increases the interface circuit efficiency. In our evaluations with two BNN architectures, using LTA reduces the area by 42x and 54x, the energy by 2.7x and 4.2x, and the latency by 3.8x and 1.15x, compared to the state-of-the-art crossbar-based BNN accelerators.	de
dc.identifier.uri	http://hdl.handle.net/2003/42564
dc.identifier.uri	http://dx.doi.org/10.17877/DE290R-24400
dc.language.iso	en	de
dc.relation.ispartofseries	IEEE journal on emerging and selected topics in circuits and systems;13(4)
dc.rights.uri	https://creativecommons.org/licenses/by/4.0/	de
dc.subject	registers	de
dc.subject	neurons	de
dc.subject	logic gates	de
dc.subject	computer architecture	de
dc.subject	artificial neural networks	de
dc.subject	FeFETs	de
dc.subject	convolution	de
dc.subject.ddc	004
dc.subject.rswk	Register <Informatik>	de
dc.subject.rswk	Neuronales Netz	de
dc.subject.rswk	Logische Schaltung	de
dc.subject.rswk	Computerarchitektur	de
dc.subject.rswk	Ferroelektrischer Transistor	de
dc.title	Unlocking efficiency in BNNs: global by local thresholding for analog-based HW accelerators	de
dc.type	Text	de
dc.type.publicationtype	Article	de
dcterms.accessRights	open access
eldorado.secondarypublication	true	de
eldorado.secondarypublication.primarycitation	M. Yayla, F. Frustaci, F. Spagnolo, J. -J. Chen and H. Amrouch, "Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-Based HW Accelerators," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 13, no. 4, pp. 940-955, Dec. 2023, doi: 10.1109/JETCAS.2023.3315561	de
eldorado.secondarypublication.primaryidentifier	https://doi.org/10.1109/jetcas.2023.3315561	de

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