Arbeitsgebiet Datentechnik

Permanent URI for this collection

http://hdl.handle.net/2003/130

Browse

Now showing 1 - 5 of 5

Convex optimization for detection in structured communication problems
(2012-12-10) Morsy, Tharwat Elsayed Hamad; Götze, Jürgen; Wöhler, Christian
The receiver in a wireless communication system has the task of computing good estimates for the data symbols that have been transmitted. The best (optimum) detector is the Maximum Likelihood (ML) detector. However, it requires a high computational complexity. This work aims to efficiently detect the transmitted symbols with a reduced complexity. In order to produce a near optimum receiver, two methods are presented. These methods are obtained by convex optimization relaxations which yield global optimum solutions. The relaxations are combined with the idea of using the structure of the channel matrix to reduce the computational complexity. The channel matrix exhibits a banded Toeplitz structure. In each case, the dual problem of the convex optimization relaxation is solved to estimate the noise power. Gradient descent algorithm is used to solve the dual problem in the first relaxation while the bisection method is applied for the second relaxation. In both cases, the result is a Generalized Minimum Mean Squared Error (GMMSE) detector which has a form similar to the Minimum Mean Square Error (MMSE) detector and a performance almost the same as the MMSE detector, but it is not require the knowledge of the noise power. The GMMSE detectors can be used in scenarios where adapted or blind adaptive detection is not suitable, for instance when the channel is rapidly changing. Using a circular approximation of banded Toeplitz matrix the Fast Fourier Transform (FFT) can be applied to reduce the computational complexity of the detectors. Finally, the local search method is applied to enhance the performance of the proposed GMMSE detector. The proposed detector is a near optimum detector with low computational complexity.
Robust watermarking and its applications to communication problems
(2012-05-14) Samee, Muhammad Kashif; Götze, Jürgen; Wietfeld, Christian
Digital watermarking has recently gained an intense interest in research and applications. An invisible and secret signal, called watermark, is added to the host data. With the help of this watermark issuer of the data can be unveiled, unauthorised users can be identified, illicit copying can be avoided, any attempt to temper with the data can be detected and many other security services can be provided. In this thesis, the relations and differences between watermarking and communication systems are elaborated. Based on these results new methods for both watermarking and communication are derived. A new blind, robust and reversible watermarking scheme based on Code Division Multiple Access (CDMA) is presented in this thesis. Using this scheme watermark is arithmetically added to spatial domain or frequency domain. Watermark is extracted by using spreading codes only. Proposed watermarking scheme is simple, computationally efficient and can be applied to any image format. A novel idea that watermark can be part of the image is presented. By using watermark, which is a part of an image, digital watermarking can be used beyond simple security tasks. A part of an image is selected and embedded in the whole image as watermark. This watermarked image is attacked (transmitted or compressed). By using the extracted watermark and attacked selected part image quality can be assessed or jpeg quantization ratio can be estimated or even image can be equalized blindly. Furthermore, CDMA based watermarking is used to authenticate radio frequency signal. Spreaded watermark is added in the form of noise to the modulated radio frequency signal. If this noise is increased, watermarked signal automatically becomes a scrambled signal. Later watermark is extracted and by using reversibility of proposed scheme watermark is removed. Once the watermarked is removed original signal is restored, hence descrambled.
VLSI design concepts for iterative algorithms
(2011-04-28) Sun, Chi-Chia; Götze, Jürgen; Kays, Rüdiger
Circuit design becomes more and more complicated, especially when the Very Large Scale Integration (VLSI) manufacturing technology node keeps shrinking down to nanoscale level. New challenges come up such as an increasing gap between the design productivity and the Moore’s Law. Leakage power becomes a major factor of the power consumption and traditional shared bus transmission is the critical bottleneck in the billion transistors Multi-Processor System–on–Chip (MPSoC) designs. These issues lead us to discuss the impact on the design of iterative algorithms. This thesis presents several strategies that satisfy various design con- straints, which can be used to explore superior solutions for the circuit design of iterative algorithms. Four selected examples of iterative al- gorithms are elaborated in this respect: hardware implementation of COordinate Rotation DIgital Computer (CORDIC) processor for sig- nal processing, configurable DCT and integer transformations based CORDIC algorithm for image/video compression, parallel Jacobi Eigen- value Decomposition (EVD) method with arbitrary iterations for com- munication, and acceleration of parallel Sparse Matrix–Vector Multipli- cation (SMVM) operations based Network–on–Chip (NoC) for solving systems of linear equations. These four applications of iterative meth- ods have been chosen since they cover a wide area of current signal processing tasks. Each method has its own unique design criteria when it comes to the direct implementation on the circuit level. Therefore, a balanced solution between various design tradeoffs is elaborated for each method. These tradeoffs are between throughput and power consumption, com- putational complexity and transformation accuracy, the number of in- ner/outer iterations and energy consumption, data structure and net- work topology. It is shown that all of these algorithms can be imple- mented on FPGA devices or as ASICs efficiently.
Systementwurf mit Zuverlässigkeitsinformation für mobile Festplatten mit hoher Datendichte
(Universität Dortmund, 2004-07-16) Schmermbeck, Stefan; Schwiegelshohn, Uwe; Wehn, Norbert
Der zunehmende Einsatz von Festplatten in mobilen Geräten erfordert neue Entwurfsmethoden. Zu den Zielen bei der Entwicklung einer Festplatte für den stationären Betrieb, wie Signalzuverlässigkeit, Speicherkapazität, Datenübertragungsrate und Kosten, kommt mit der Verlustleistung der eingesetzten Schaltungen ein weiterer Parameter hinzu. In dieser Arbeit wird ein Konzept für den Entwurf der signalverarbeitenden Komponenten einer mobilen Festplatte, dem so genannten Lesekanal, präsentiert. Da die Entwicklungsziele im Konflikt zueinander stehen, wird ein systemübergreifender Ansatz gewählt, bei dem die Abhängigkeiten zwischen den unterschiedlichen Zielen berücksichtigt werden. Um wachsenden Anforderungen an die Signalzuverlässigkeit aufgrund immens steigender Datendichten gerecht zu werden, wird bei den eingesetzten Verfahren die so genannte Zuverlässigkeitinformation verwendet. Diese während der Detektion berechnete Zusatzinformation ist ein Maß für die Fehlerwahrscheinlichkeit der gelesenen Daten. Mit ihrer Hilfe kann die Leistung der eingesetzten Algorithmen verbessert und dadurch die Fehlerrate deutlich abgesenkt werden. Der Nachteil dieses Verfahrens liegt jedoch in der hohen Komplexität der eingesetzten Algorithmen, die darüber hinaus an die Besonderheiten eines magnetischen Kanals angepasst werden müssen. In dieser Arbeit werden verschiedene Varianten zur Integration von Zuverlässigkeitsinformation in einen magnetischen Kanal verfolgt, bei denen die Komplexität der eingesetzten Algorithmen und Schaltungen so gering wie möglich gehalten werden soll. Zu diesem Zweck werden bekannte, verlustleistungsarme Verfahren zum Teil um die Fähigkeit zur Ausgabe oder Weiterverarbeitung von Zuverlässigkeitsinformation erweitert oder existierende Verfahren für die Verwendung auf dem magnetischen Kanal optimiert. Mit einem systemübergreifenden Ansatz wird ein Lesekanal entworfen, bei dem die Komplexitätserhöhung aufgrund der Modifikationen an anderer Stelle durch Vereinfachungen wieder kompensiert wird. Neben dem leistungsfähigen Konzept der Signalraumdetektion, das um die Ausgabe von Zuverlässigkeitsinformation erweitert wird, kommen die bei Datenspeichern weit verbreiteten, fehlerkorrigierenden Reed-Solomon Codes zum Einsatz. Ein zusätzlicher, innerer Parity-Check Code dient sowohl als Modulationscode, als auch - in Verbindung mit der Zuverlässigkeitsinformation des Detektors - zur Verbesserung der Fehlerkorrektur. Der vorgestellte Kanal erreicht durch diese Ma?nahmen eine deutlich niedrigere Fehlerrate. Des Weiteren wird die Eignung für zukünftige mobile Festplatten gezeigt, da der Lesekanal unempfindlich auf die bei hohen Datendichten verstärkt auftretenden Störgrößen, wie zum Beispiel Transitionsrauschen, reagiert.
Design and evaluation of job scheduling strategies for grid computing
(Universität Dortmund, 2002-11-22) Yahyapour, Ramin; Schwiegelshohn, Uwe; Monien, Burkhard
Grid computing is intended to offer an easy and seamless access to remote resources. The scheduling task of allocating these resources automatically to user jobs is an essential part of a grid environment. This work discusses the evaluation and design of different scheduling strategies. A concept for the design process of such a scheduling system is presented. The evaluation of scheduling algorithms for single parallel machines is done by theoretical analysis and by simulation experiments. The theoretical approach by competitive analysis lead to bounds for the worst-case scenarios. As there is great interest in the scheduling performance of a real system installation, simulations have been applied for further evaluation. In addition to the theoretical analysis, the presented preemptive scheduling algorithm is also effcient in terms of makespan and average response time in a real system scenario if compared to other scheduling algorithms. In some of the examined scenarios the algorithm could outperform other common algorithms such as backfilling. Based on these results, scheduling algorithms for the grid environment have been developed. On one hand, these methods base on modifications of the examined conventional scheduling strategies for single parallel machines. On the other hand, a scheduling strategy with a market economic approach is presented. As a proof of concept a possible architecture of a scheduling environment is presented, which has been used for the evaluation of the presented algorithms. The work ends with a brief conclusion on the discussed scheduling strategies and gives an outlook on future work.

Browse

Recent Submissions