Lehrstuhl für Mikro- und Nanoelektronik
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Item Buried graphene heterostructures for electrostatic doping of low-dimensional materials(2023-04-13) Gumprich, A.; Liedtke, J.; Beck, S.; Chirca, I.; Potočnik, T.; Alexander-Webber, J. A.; Hofmann, S.; Tappertzhofen, S.The fabrication and characterization of steep slope transistor devices based on low-dimensional materials requires precise electrostatic doping profiles with steep spatial gradients in order to maintain maximum control over the channel. In this proof-of-concept study we present a versatile graphene heterostructure platform with three buried individually addressable gate electrodes. The platform is based on a vertical stack of embedded titanium and graphene separated by an intermediate oxide to provide an almost planar surface. We demonstrate the functionality and advantages of the platform by exploring transfer and output characteristics at different temperatures of carbon nanotube field-effect transistors with different electrostatic doping configurations. Furthermore, we back up the concept with finite element simulations to investigate the surface potential. The presented heterostructure is an ideal platform for analysis of electrostatic doping of low-dimensional materials for novel low-power transistor devices.Item Programmable mixed-signal circuits(2023-11-16) Tappertzhofen, StefanA novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint signal routing switches with small resistance and capacity. As a proof-of-concept, LT Spice simulations of digital and analogue example circuits implemented by the new concept are demonstrated. It is discussed how important design parameters can be tuned in the circuity. Compared to competing technologies such as Field Programmable Analogue Arrays or Application-Specific Integrated Circuits, the presented concept allows for development of ultra-flexible, reconfigurable, and cheap embedded mixed-signal circuits for applications where only limited space is available or high bandwidth is required.Item Transfer-free graphene passivation of sub 100 nm thin Pt and Pt–Cu electrodes for memristive devices(2023-02-24) Tappertzhofen, Stefan; Braeuninger-Weimer, P.; Gumprich, Alexander; Chirca, I.; Potočnik, T.; Alexander-Webber, J. A.; Hofmann, S.Memristive switches are among the most promising building blocks for future neuromorphic computing. These devices are based on a complex interplay of redox reactions on the nanoscale. Nanoionic phenomena enable non-linear and low-power resistance transition in ultra-short programming times. However, when not controlled, the same electrochemical reactions can result in device degradation and instability over time. Two-dimensional barriers have been suggested to precisely manipulate the nanoionic processes. But fabrication-friendly integration of these materials in memristive devices is challenging.Here we report on a novel process for graphene passivation of thin platinum and platinum/copper electrodes. We also studied the level of defects of graphene after deposition of selected oxides that are relevant for memristive switching.Item Fabrication of steep slope carbon nanotube transistors on novel multi-gate substrates(2023) Gumprich, Alexander; Tappertzhofen, Stefan; Knoch, JoachimThe need for highly integrated low-power transistors has rapidly increased over the last decades. The very effective downscaling and optimization of metal-oxide-semiconductor field-effect transistors (MOSFETs) have initiated the advanced technological environment of today. However, the physical limitations of those devices are restricting its further development to a certain point which has already been reached or will be in the very near future. The thesis focuses on steep slope transistor technology, designated to potentially replace MOSFET architectures. The work includes the design and fabrication of a so-called buried triple gate platform (BTG), integrating three graphene/metal gates to implement individually adjustable electrostatic doping profiles. The wafer-scaled manufacturing process involves optical lithography, physical and chemical vapor deposition techniques, reactive ion etching and wet etching structuring procedures. With the deposition of carbon nanotubes and the subsequent connection to source and drain terminals, Tunnel-FET devices are fabricated to demonstrate the feasibility of the architecture. Moreover, similar devices called energy filtering FETs are manufactured using an existing buried multi gate platform (BMG). Providing 17 mutually insulated and individually addressable gates, the platform enables the generation of periodic potential barriers creating a so-called superlattice. The emerging miniband allows for tunneling at low energies while preventing hot electron injection from the Boltzmann tail, hence the term energy filtering FET. The final fabrication of the transistors is carried out by high-resolution electron-beam lithography on either platform. Subsequent static electrical measurements demonstrate transistor characteristics and the working principle of the architectures for electrostatic doping of low- dimensional materials. Both platforms are universal and can be used for application and analysis of electrostatic doping of various 1D and 2D materials. The achieved results in this work can be considered to be a successful validation of the concept for steep slope transistor devices with the potential to obtain a central role in future low-power applications.Item Impact of electrode materials on the performance of amorphous IGZO thin-film transistors(2022-06-15) Tappertzhofen, StefanThis study reports on the fabrication and characterization of thin-film transistors (TFTs) based on indium–gallium–zinc–oxide (IGZO) with various source- and drain-region metals (Pt, W and Ti). The performance of the IGZO transistors is compared to TFTs based on hydrogenated amorphous silicon (a-Si:H) with Pt source- and drain-regions. From the output characteristics maximum saturation mobilities of µ = 0.45 cm2/Vs for a-Si:H, and µ = 24 to 50 cm2/Vs for IGZO TFTs are extracted, which are competitive to high-performance thin-film transistors. The study reveals a general influence of the source- and drain-electrode material on the maximum saturation mobility and inverse sub-threshold slope.Item Research data supporting "Programmable Mixed-Signal Circuits"(2023-05-16) Tappertzhofen, StefanResearch data supporting "Programmable Mixed-Signal Circuits". This file contains all raw LT Spice simulation files and the measurement of the resisitive switching curve.Item Research data supporting "Buried Graphene Heterostructures for Electrostatic Doping of Low-Dimensional Materials"(2023-02-06) Gumprich, Alexander; Tappertzhofen, StefanResearch data supporting "Buried Graphene Heterostructures for Electrostatic Doping of Low-Dimensional Materials" by A. Gumprich et al. The data included electrical measurements, raman spectra and simulation results.Item Concept of an efficient self-startup voltage converter with dynamic maximum power point tracking for microscale thermoelectric generators(2022-04-25) Merten, D.; Singer, J. A.; Fiedler, H.; Tappertzhofen, S.Microscale Thermoelectric Generators (microTEGs) have a high application potential for energy harvesting for autonomous microsystems. In contrast to conventional thermoelectric generators, microTEGs can only supply small output-voltages. Therefore, voltage converters are required to provide supply-voltages that are sufficiently high to power microelectronics. However, for high conversion efficiency, voltage converters need to be optimized for the limited input voltage range and the typically high internal resistance of microTEGs. To overcome the limitations of conventional voltage converters we present an optimized self-startup voltage converter with dynamic maximum power point tracking. The performance potential of our concept is theoretically and experimentally analyzed. The voltage conversion interface demonstrates energy harvesting from open-circuit voltages as low as 30.7 mV, and enables independent and full start-up from 131 mV. No additional external power supply is required at any time during operation. It can be operated with a wide range of internal resistances from 20.6 to − 4 kΩ with a conversation efficiency between η = 68–79%.